The performance of semiconductor integrated circuits had been enhanced by integrating more transistors in one chip (semiconductor substrate) with the progress of micromachining techniques. However, the way to increase the scale of integration of one chip as embraced in the past has not necessarily been a most appropriate solution because of the limit of scaling-down or the influence of increase in the cost for using cutting-edge processes. Therefore, three-dimensional integration, by which more than one semiconductor integrated circuit is stacked in three-dimensional directions, has been a promising technique. For enhancement in the performance of semiconductor integrated circuits by the three-dimensional integration, which is herein also referred to as “3D integration” or “3D stacking”, a mechanism for performing high-speed and large-capacity communication between stacked semiconductor integrated circuits is required. In addition, the power needed for such communication reaches a considerable level with respect to power consumption by processors and the like. Therefore, a technique for a high-speed and large-capacity communication between semiconductor integrated circuits, especially including a method for executing such communication with a smaller power is made a technique with overriding priority for 3D integration of semiconductor integrated circuits.
As communication systems for stacked semiconductor integrated circuits, wired and wireless systems have been studied. As possible wired systems, there are a system including formation of a via-hole in a silicon substrate of a semiconductor integrated circuit, and a system including wire bonding. However, the former one is limited in the scene where it can be used because formation of a via-hole in a silicon substrate poses a burden in manufacturing process; the latter one is smaller in the effect of 3D stacking in terms of performance and power because of longer wiring. On the other hand, systems that communication is performed by wireless are expected as a useful method for a scene where any wired system cannot be used because of the problems as described above.
In the typical wireless communication used for communication between mobile phones and base stations, wireless LAN and the like, a transmitter sends data after having executed some kind of modulation on the data, and a receiver-side LSI performs sampling at a rate sufficiently higher than the rate of transmitted data, and executes computation on the data thus sampled thereby to reproduce the transmitted data. However, this method involves a larger volume of computation and a greater amount of power consumption, and takes a longer time until a receiving party accepts data. On this account, such method suffices for an application scene that a larger amount of cost may be devoted because of a larger communication field. However it is unsuitable for communication in an extremely near field like between stacked semiconductor integrated circuits because of its excessively large overhead.
Wireless communication techniques which are suitable for communication in a near field like between 3D-stacked semiconductor integrated circuits, and offer smaller overheads are described in the following four patent documents: JP-A-2005-228981, JP-A-2006-50354, JP-A-2006-173415, and JP-A-2006-173986.
In cases of communication between 3D-stacked semiconductor integrated circuits, it is thought advisable to arrange a communication device so that the timing of a communicating operation can be adjusted. This is because individual semiconductor integrated circuits have variations in manufacturing and are influenced by changes of operating conditions including a temperature and an operating source voltage. JP-A-2002-223204 discloses a technique for wired communication, by which an arrangement for correcting a transmission property is adopted on the side of a receiver.